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[ak4420] 192khz 24-bit stereo ? dac with 2vrms output ak4420 general description the ak4420 is a 5v 24-bit stereo dac with an int egrated 2vrms output buffer. a charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2vrms output. using akm?s multi bit modulator architecture, t he ak4420 delivers a wide dynamic range while preserving linearity for improved thd+n perform ance. the ak4420 integrates a combination of sw itched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. the 24-bit word length and 192khz sampling rate make this part ideal for a wide range of consumer audio applications, such as dvd, av re ceiver system and set-top boxes. the ak4420 is offered in a space saving 16pin tssop package. features ? sampling rate ranging from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24-bit 8 times fir digital filter ? switched-capacitor filter with high tolerance to clock jitter ? single ended 2vrms output buffer ? digital de-emphasis ? soft mute ? i/f format: 24-bit msb justified or i 2 s ? master clock: 512fs, 768fs or 1152fs (normal speed mode) 256fs or 384fs (double speed mode) 128fs, 192fs (quad speed mode) ? thd+n: -92db ? dynamic range: 105db ? automatic power-on reset circuit ? power supply: +4.5 +5.5v ? ta = -20 to 85 c ? small package: 16pin tssop (6.4mm x 5.0mm) dif lrck bick sdti audio data interface mclk ? modulator aoutl 8x interpolator scf lpf aoutr vdd vss1 control interface clock divider ? 8x interpolator scf lpf charge pump cp cn vee vss2 cvdd 1 1 dzf smute modulator ms0683-e-02 2007/12 - 1 -
[ak4420] ordering guide ak4420et -20 +85 c 16pin tssop (0.65mm pitch) AKD4420 evaluation board for ak4420 pin layout 6 5 4 3 2 1 cn cp mclk smute bick sdti 7 dif 8 vee vss2 cvdd dzf vss1 vdd aoutl aoutr ak4420 top view 11 12 13 14 15 16 10 9 lrck ms0683-e-02 2007/12 - 2 -
[ak4420] pin/function no. pin name i/o function 1 cn i negative charge pump capacitor terminal pin connect to cp with a 1.0 f capacitor that should have the low esr ( equivalent series resistance ) over all temperature range. when this capacitor has the polarity, the positive polar ity pin should be connected to the cp pin. non polarity capacitors can also be used. 2 cp i positive charge pump capacitor terminal pin connect to cn with a 1.0 f capacitor that should have the low esr ( equivalent series resistance ) over all temperature range. when this capacitor has the polarity, the positive polar ity pin should be connected to the cp pin. non polarity capacitors can also be used. 3 smute i soft mute enable pin (internal pull down: 100k ? ) ?h?: enable, ?l?: disable 4 mclk i master clock input pin an external ttl clock shoul d be input on this pin. 5 bick i audio serial data clock pin 6 sdti i audio serial data input pin 7 lrck i l/r clock pin 8 dif i audio data interface format pin ?l?: left justified, ?h?: i2s 9 aoutr o rch analog output pin when power down, outputs vss(0v, typ). 10 aoutl o lch analog output pin when power down, outputs vss(0v, typ). 11 vdd - dac power supply pin: 4.5v 5.5v 12 vss1 - ground pin1 13 dzf o zero input detect pin 14 cvdd - charge pump power supply pin: 4.5v 5.5v 15 vss2 - ground pin2 16 vee o negative voltage output pin connect to vss2 with a 1.0 f capacitor that should have the low esr ( equivalent series resistance ) over all temperature range. when this capacitor has the polarity, the positive polar ity pin should be connected to the vss2 pin. non polarity capacitors can also be used. note: all input pins except for the cn pin should not be left floating. ms0683-e-02 2007/12 - 3 -
[ak4420] absolute maximum ratings (vss1=vss2=0v; note 1 ) parameter symbol min max units power supply vdd cvdd -0.3 -0.3 +6.0 +6.0 v v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. vss1, vss2 connect to the same analog grand. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 1 ) parameter symbol min typ max units power supply vdd cvdd +4.5 +5.0 vdd +5.5 v note 3. cvdd should be equal to vdd *akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. ms0683-e-02 2007/12 - 4 -
[ak4420] analog characteristics (ta = 25 c; vdd=cvdd = +5.0v; fs = 44.1 khz; bick = 64fs; signal frequency = 1 khz; 24bit input data; measurement frequency = 20hz 20khz; r l 5k ) parameter min typ max units resolution 24 bits dynamic characteristics ( note 4 ) fs=44.1khz, bw=20khz -92 -84 db fs=96khz, bw=40khz -92 - db thd+n (0dbfs) fs=192khz, bw=40khz -92 - db dynamic range (-60dbfs with a-weighted. ( note 5 ) 98 105 db s/n (a-weighted. ( note 6 ) 98 105 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy dc offset (at output pin) -60 0 +60 mv gain drift 100 - ppm/ c output voltage ( note 7 ) 1.97 2.12 2.27 vrms load capacitance ( note 8 ) 25 pf load resistance 5 k power supplies power supply current: ( note 9 ) normal operation (fs 96khz) normal operation (fs=192khz) power-down mode ( note 10 ) 24 27 10 36 40 100 ma ma a note 4. measured by audio precision (system two). refer to the evaluation board manual. note 5. 98db for 16bit input data note 6. s/n does not depend on input data size. note 7. full-scale voltage (0db). output voltage is proportional to the voltage of vdd, aout (typ.@0db) = 2.12vrms vdd/5. note 8. in case of driving capacitive load, inset a resistor between the output pin and the capacitive load. note 9. the current into vdd and cvdd. note 10. all digital inputs including clock pins (mclk, bick and lrck) are fixed to vss or vdd ms0683-e-02 2007/12 - 5 -
[ak4420] filter characteristics (ta = 25 c; vdd=cvdd = +4.5 +5.5v; fs = 44.1 khz) parameter symbol min typ max units digital filter passband 0.05db ( note 11 ) ?6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 11 ) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 12 ) gd - 19.3 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.05 0.05 0.05 - - - db db db note 11. the passband and stopband frequencie s scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 12. calculated delay time caused by digital filte r. this time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. dc characteristics (ta = 25 c; vdd=cvdd = +4.5 +5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level input voltage (iout = -80ua) low-level input voltage (iout = 80ua) vih vil vdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a note 13. the smute pin is not included. the smute pin has internal pull-up resistor (typ.100k ? ) . ms0683-e-02 2007/12 - 6 -
[ak4420] switching characteristics (ta = 25 c; vdd=cvdd = +4.5 +5.5v) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 4.096 30 11.2896 36.864 70 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 32 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high bick ? ? to lrck edge ( note 14 ) lrck edge to bick ? ? ( note 14 ) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns note 14. bick rising edge must not occur at the same time as lrck edge. ms0683-e-02 2007/12 - 7 -
[ak4420] timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 1. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 2. serial interface timing ms0683-e-02 2007/12 - 8 -
[ak4420] operation overview system clock the external clocks required to operate the ak4420 are mc lk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. sampling speed and mclk frequency are detected automatically and then the internal master clock is set to the appropriate frequency ( table 1 ). the ak4420 is automatically placed in power saving mode when mclk and lrck stop during normal operation mode, and the analog output is forced to 0v(typ). when mclk and lrck are input again, the ak4420 is powered up. after power-up, the ak4420 is in the power-down mode until mclk and lrck are input. lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 32.0khz 8.192 12.288 44.1khz 11.2896 16.9344 48.0khz 12.288 18.432 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - quad 192.0khz 24.5760 36.8640 - - - - - table 1. system clock example when mclk= 256fs/384fs, the ak4420 supports sampling rate of 32khz~96khz ( table 2 ). but, when the sampling rate is 32khz~48khz, dr and s/n will degr ade by approximately 3db as comp ared to when mclk= 512fs/768fs. mclk dr,s/n 256fs/384fs 102db 512fs/768fs 105db table 2. relationship between mclk frequency and dr, s/n (fs= 44.1khz) audio serial interface format the audio data is shifted in via the sdti pin using the bick and lrck inputs. the dif pin can select between two serial data modes as shown in table 3 . in all modes the serial data is msb-first, two?s complement format and it is latched on the rising edge of bick. in one cycle of lrck, eight ?h? pulses or more must not be input to the dif pin. mode dif sdti format bick figure 0 l 24bit msb justified 48fs figure 3 1 h 24bit i 2 s figure 4 48fs table 3. audio data formats ms0683-e-02 2007/12 - 9 -
[ak4420] lrck bick ( 64fs ) sdti 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0don?t care 23 22 23 figure 3. mode 0 timing lrck bick ( 64fs ) sdti 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 22 4 23 25 22 1 0 don?t care 23 23 figure 4. mode 1 timing zero detect function when the input data for both channels are continuously zeros for 8192 lrck cycles, the dzf pin is set to ?h?. the dzf pin immediately is set to ?l? if the input data for both channels are not zero after going to dzf ?h?. ms0683-e-02 2007/12 - 10 -
[ak4420] analog output block the internal negative power supply generation circuit ( figure 5 ) provides a negative power supply for the internal 2vrms amplifier. it allows the ak4420 to output an audio signal centered at vss (0v, typ) as shown in figure 6 . the negative power generation circuit ( figure 5 ) needs 1.0uf capacitors (ca, cb) with low esr (equivalent series resistance). if this capacitor is polarized, the positive polarity pin should be connected to the cp and vss2 pins. this circuit operates by clocks generated from mclk. when mclk stops, the ak4420 is placed in the rese t mode automatically and the analog outputs settle to vss (0v, typ). cvdd charge pump cp cn vss2 vee 1uf 1uf negative power a k4420 (+) cb ca (+) figure 5. negative power generation circuit a outr a k4420 (aoutl) 0v 2.12vrms figure 6. audio signal output ms0683-e-02 2007/12 - 11 -
[ak4420] soft mute operation soft mute operation is performed in the digital domain. when the smute pin is set ?h?, the output signal is attenuated to - in 1024 lrck cycles. when the smute pin is returned to ?l?, the mute is cancelled and the output attenuation gradually changes to 0db in 1024 lrck cycles. if the soft mute is cancelled within the 1024 lrck cycles after starting this operation, the attenuation is discontinued and it is returned to 0db by the same cycle. soft mute is effective for changing the signal source without stopping the signal transmission. smute pin a ttenuation dzf pin 1024/fs 0db - a out 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the time for input data be attenuation to - , is normal speed mode: 1024 lrck cycles (1020/fs). double speed mode: 2048 lrck cycles (2048/fs). quad speed mode : 4096 lrck cycles (4096/fs). (2) the analog output corresponding to a specific digital input has a group delay, gd. (3) if soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level in the same cycle. (4) when the input data for both channels are continuously zeros for 8192 lrck cycles, the dzf pin is set to ?h?. the dzf pin immediately is set to ?l? if the input data are not zero after going to dzf ?h?. figure 7. soft mute and zero detect function ms0683-e-02 2007/12 - 12 -
[ak4420] system reset the ak4420 is in power down mode upon power-up. the mlck should be input after the power supplies are ramped up. the ak4420 is in power-down mode until lrck are input. d/a out (analog) mclk dzf 20 us low power supply (vdd, cvdd) 2, 3 lrck digital circuit analog circuit charge pump circuit charge pump counter circuit time a (1) (2) (3) (5) power-up power-up ?0? data d/a in ( di g ital ) mute ( d/a out ) (4) (6) power down power down power-up power down notes: (1) approximately 20us after a mclk input is detected, the internal analog circuit is powered-up. (2) the digital circuit is powered-up after 2 or 3 lrck cycles following the detection of mclk. (3) the charge pump counter starts after the charge pump circuit is powered-up. the dac outputs a valid analog signal after time a. time a = 1024/ (fs x 16): normal speed mode time a = 1024/ (fs x 8) : double speed mode time a = 1024/ (fs x 4) : quadruple speed mode (4) no audible click noise occurs under normal conditions. (5) the dzf pin is ?l? in the power-down mode. (6) the power supply must be powered-up when the mclk pin is ?l?. mclk must be input after 20us when the power supply voltage achieves 80% of vdd. if not, click noise may occur at a different time from this figure. figure 8. system reset diagram ms0683-e-02 2007/12 - 13 -
[ak4420] reset function when the mclk or lrck stops, the ak4420 is placed in reset mode and its analog outputs are set to vss (0v, typ). when the mclk and lrck are restarted, the ak4420 returns to normal operation mode. the bick can be stopped when mclk or lrck is stopped, but it must not be stopped when mclk and lrck are supplied. normal operation internal state reset normal operati on gd d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (1) vss (2) mclk stop (3) (3) (4) clock in mclk, bick, lrck lrck stop (4) (5) dzf (6) dzf (6) notes: (1) digital data can be stopped. the click noise after mclk and lrck are input again can be reduced by inputting the ?0? data during this period. (2) the analog output corresponding to a specific digital input has group delay (gd). (3) no audible click noise o ccurs under normal conditions. (4) clocks (mclk, bick, lrck) can be stopped in the reset mode (mclk or lrck is stopped). (5) the ak4420 detects the stop of lrck if lrck stops for more than 2048/fs. when lrck is stopped, the ak4420 exits reset mode after lrck is inputted.. (6) the dzf pin is set to ?l? in the reset mode. figure 9. reset timing example ms0683-e-02 2007/12 - 14 -
[ak4420] system design figure 10 shows the system connection diagram. an evaluation boa rd (AKD4420) is available for fast evaluation as well as suggestions for peripheral circuitry. analog 5.0v 24bit audio data 1u (1) 64fs master clock external mute circuits analog ground digital ground + mode- setting ak4420 dif sdti bick mclk smute cp cn lrck aoutr aoutl vdd vss1 dzf cvdd vss2 vee 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + + fs 1u (1) 0.1u 10u + 0.1u 10u lch out rch out 10? note: use low esr (equivalent series resistance) capacitors. when using polarized capacitors, the positive polarity pin should be connected to the cp and vss2 pin. vss1 and vss2 should be separated from digital system ground. digital input pins should not be allowed to float. figure 10. typical connection diagram ms0683-e-02 2007/12 - 15 -
[ak4420] 1. grounding and power supply decoupling vdd, cvdd and vss are supplied from the analog supply and should be separated from the system digital supply. decoupling capacitors, especially 0.1 f ceramic capacitors for high frequency by pass, should be placed as near to vdd and cvdd as possible. the differe ntial voltage between vdd and vss pins set the analog output range. the power-up sequence between vdd and cvdd is not critical. 2. analog outputs the analog outputs are single-ended and centered around the v ss (ground) voltage. the output signal range is typically 2.12vrms (typ @vdd=5v). the internal switched-capacitor filter (scf) and con tinuous-time filter (ctf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. using single a 1 st -order lpf ( figure 11 ) can reduce noise beyond the audio passband. figure 12 shows example in the case of 10k ? , 100k ? terminus. the output voltage is a positive full scale for 7fffffh (@24bit data) and a negative full scale for 800000h (@24bit data). the ideal output is 0v (vss) voltage for 000000h (@24bit data). the dc offset is 60mv or less. aout 470 2.2nf ak4420 2.12vrms (typ) analog out (fc = 154khz, gain = -0.28db @ 40khz, gain = -1.04db @ 80khz) figure 11. external 1 st order lpf circuit example1 aout 820 1000pf ak4420 analog out 220 10k ? 1.92vrms (typ) 100k ? 2.1vrms (typ) 47 47k figure 12. external 1 st order lpf circuit example2 ms0683-e-02 2007/12 - 16 -
[ak4420] package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.05 0.05 a 1 8 9 16 16 p in tssop ( unit: mm ) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate ms0683-e-02 2007/12 - 17 -
[ak4420] marking akm 4420et xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4420et 4) asahi kasei logo revision history date (yy/mm/dd) revision reason page contents 07/11/05 00 first edition 07/12/04 01 13 figure 8. the description of the click noise was corrected. error correction 14 figure 9. the description of the click noise was corrected. 07/12/17 02 error correction 14 ?the bick can be stopped when mclk or lrck is stopped, but it must not be stopped when mclk and lrck are supplied.? was deleted. ms0683-e-02 2007/12 - 18 -
[ak4420] important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. ms0683-e-02 2007/12 - 19 -

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